The invention concerns generally the technology of converting electric signals oscillating on a certain relatively high frequency into certain other electric signals oscillating on a certain different relatively high frequency. Especially the invention concerns the use of a fractional prescaler with multiple divisor numbers for the above-mentioned purpose.
FIG. 1 illustrates a known circuit topology for generating oscillating signals with a certain predefined frequency. The circuit topology is known as one embodiment of the PLL or phase-locked loop concept. The component which generates the actual oscillating output signal fout is a VCO or voltage-controlled oscillator 101. From the output there is a feedback connection to a prescaler 102 which converts the oscillating output signal fout into another oscillating signal fdiv with a lower frequency. To be exact, the frequency of the oscillating signal fdiv is a fraction of that of the oscillating output signal fout, i.e. the prescaler 102 divides the signal fout with a certain divisor or modulus. The lower frequency signal fdiv is fed into a phase detector 103 together with a very stable reference frequency fref. The phase detector 103 gives a difference signal which depends on the phase difference between its input signals fdiv and fref. This difference signal is filtered in a low-pass type loop filter 104 to get a control voltage signal to the VCO 101. A mode selection signal Mode coupled to the prescaler 102 determines the divisor to be used. A typical known prescaler type is the so-called dual modulus prescaler where the mode selection signal Mode has two allowed values so that when the mode selection signal has its first value a divisor N is used and when the mode selection signal has its second value a divisor N+1 is used.
FIG. 2 illustrates a known conventional dual-modulus prescaler architecture. It consists of a first divider 201 known as the synchronous divider and a second divider 202 known as the asynchronous divider as well as of some logical gates. Each divider comprises a chain of D-flip-flops. Note that in order to preserve consistency with FIG. 1 there appears a signal fout which is the input signal of the prescaler while its output is denoted as fdiv.
The synchronous divider 201 operates at full frequency, which means that all three flip-flops 203, 204 and 205 are clocked by the input signal fout the frequency of which may be in the order of hundreds of MHz. Most of the time the mode selection signal Mode is low so the intermediate frequency fint on line 206 is determined by the loop of the first two flip-flops 203 and 204 in the synchronous divider 201. During such times fint=fout/4, and since the effect of the asynchronous divider 202 is to divide fint by 32, the prescaler implements a divide-by-128 function, i.e. fdiv=fout/128. When the mode selection signal Mode is high and all Q-outputs from the flip-flops of the asynchronous divider 202 go high simultaneously, the control signal Ctrl on line 207 goes also high and the loop in the synchronous divider 201 is momentarily closed over three flip-flops instead of two, causing an extra delay which is equivalent to dividing by five. When the prescaler divides once by five and 31 times by four, the net effect is a division by 129, i.e. fdiv=fout/129.
The problem of the prescaler of FIG. 2 is that there are three fully functional D-flip-flops which must be continuously clocked with full frequency. Taken that CMOS technology is used for hardware implementation, a total of three D-flip-flops clocked at a very high frequency presents a substantial drain of current and a serious load to the output of the VCO in the arrangement of FIG. 1.
From the publication J. Craninckx, M. S. J. Steyaert: xe2x80x9cA 1.75-GHz/3-V Dual-Modulus Divide-by-128/129 Prescaler in 0.7 xcexcm CMOSxe2x80x9d, IEEE Journal of Solid-State Circuits, Vol. 31, No. 7, July 1996, which is incorporated herein by reference, there is known the dual-modulus prescaler architecture illustrated in FIG. 3. Here an input signal fout to the prescaler and its complementary differential pair {overscore (fout)} are fed into a divide-by-2 flip-flop 301. The resulting differential pair of signals F2 and {overscore (F2)} are once again divided by two in a second divide-by-2 flip-flop 302 which is of the known master/slave type so that it gives four output signals each of which has the frequency of one quarter that of the original frequency fout. The four output signals from the second divide-by-2 flip-flop 302 have mutual phase differences of xcfx80/2 radians so that they may be designated as F4,I; F4,Q; {overscore (F4,I)} and {overscore (F4,Q)}. They are coupled to the four input terminals of a phase selector block 303 which is just a controllable selection switch which couples one of its input signals at a time to its output. The output F4 of the phase selector block 303 is coupled to a further divide-by-32 block 304 the output of which is the output signal fdiv of the prescaler.
A frequency control block 305 commands the phase selector block 303 to either simply connect one of its input signals constantly to its output or to change the selection of input signal. Most of the time the frequency control block 305 is disabled so that the prescaler implements a divide-by-128 function, i.e. fdiv=fout/128. When the mode selection signal Mode is high, the NAND gate 306 activates the frequency control block 305 so that on every positive edge of the output signal fdiv the control signal Ctrl instructs the phase selector block 303 to pick the next input signal. This causes in the signal F4 a delay which is exactly enough to result in an overall effect according to which the prescaler now implements a divide-by-129 function, i.e. fdiv=fout/129.
The advantage of the prescaler of FIG. 3 over that of FIG. 2 is that there is only one flip-flop to be driven at the full clock frequency, which means a considerably lighter load to the output of the VCO in a PLL application and consumes much less power. However, the prescaler of FIG. 3 is rather inflexible in that only two divisors can be used. Additionally it gives rise to a very harmful spike effect which means that if the transition in changing input signals in the phase selector block 303 is too fast, an unwanted transient negative voltage spike appears in the output signal of the phase selector block 303. The authors of the reference publication propose that the spike should be eliminated by buffering a part of the control signal which controls the phase selection. To be exact, the authors suggest that a very small buffer inverter should be used to steer the control signals in order to limit their slope.
It is an object of the invention to present a prescaler architecture which enables the construction of high-speed multimodulus prescalers with low power consumption and applicability in very high clocking frequencies. An additional object of the invention is to present a prescaler architecture where the above-mentioned spike effect does not appear.
The objects of the invention are achieved by dividing an oscillating input signal into a multitude of component signals which differ in phase from each other, and using a flexibly controlled phase selector unit to compose various combinations from the component signals.
The prescaler according to the invention comprises
a component signal composer arranged to generate a number of parallel component signals that differ in phase from each other and
a controllable phase selector arranged to respond to a control signal by either selecting a constant number of unchanged ones of the parallel component signals or to repeatedly change its selection among the parallel component signals;
it is characterized in that the component signal composer is arranged to generate more than four parallel component signals for the phase selector to choose from.
The invention applies also to a frequency synthesizer which is characterized in that it comprises a prescaler of the above-defined kind.
Additionally the invention applies to a method for generating an output frequency from an input frequency, comprising the steps of
generating, on the basis of the input frequency, a number of parallel component signals that differ in phase from each other and
controllably either selecting a constant number unchanged ones of the parallel component signals or repeatedly switching the selection among the component signals;
the method according to the invention is characterized in that the step of generating a number of parallel component signals comprises the substep of generating more than four parallel component signals.
According to the present invention, a great degree of flexibility can be added to the known phase selection principle if the number of available component signals is increased from four. In a prescaler according to the invention a controllable phase selector has more than four component signals of different phase to choose from. Most advantageously it is also capable of realizing other switching modes than just picking the next component signal in the order of ascending or descending phase. This way a multitude of fractional divisions, even with non-integer dividers, can be achieved in a single hardware component.
In order to enable the controlled selection of component signal combinations in the phase selector a more advanced controlling scheme is needed than the on-off type mode selection signal in the known prescalers. An advantageous form of realising the controlling functionality is to couple the actual phase selector into a control block which accepts a digital code word as its input and converts different bit combinations in an inputted digital code word into control signals for the phase selector. One of the inputs of the control block is typically a feedback connection from the output parts of the prescaler in order to synchronize the controlled phase selection with transitions in the output signal of the prescaler.
The phase selector proper is most advantageously implemented as a differential multiplexer where each component signal drives a switch of its own so that the complementary components of the same differential input signal pair drive parallel switches which are additionally coupled in series with a common control switch for that differential input signal pair. A first loaded supply voltage rail is common to all I-phase component signals and a second loaded supply voltage rail is common to all Q-phase component signals. A common bias can be used for all switching branches. The outputs of the multiplexer are obtained from the loaded supply voltage rails.